A Four-Stage Mesochronous Synchronizer with Back-Pressure and Buffering for Short and Long Range Communications

A four-stage mesochronous synchronizer is described. It enables low latency and full throughput crossing of boundaries of same frequency, different phase clock domains. Full back pressure is supported, where the receiver can start and stop accepting words without any data loss. Variable depth buffering is provided, supporting a wide range of short and long range communications and accommodating multi-cycle wire delays. Burst data can also be accommodated thanks to buffering. Dynamic phase shifting due to varying voltage and temperature are mitigated by increasing the separation between write and read pointers. Unlike common synchronizers, this circuit is exposed to metastability risk only during reset. The synchronizer provides lower latency and higher reliability than typical two-clock FIFO and other asynchronous and mesochronous synchronizers. It is suitable for implementation using standard cell design and does not require any delay lines, tuning of clock trees and other full custom circuits. It is shown that a minimum of four buffer stages are required, in contrast with previous proposals for three stages.